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XC95144 In-System Programmable CPLD
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Product Specification
Features
* * * * * 7.5 ns pin-to-pin logic delays on all pins fCNT to 111 MHz 144 macrocells with 3,200 usable gates Up to 133 user I/O pins 5V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Function Block (FB) - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std 1149.1 boundary-scan (JTAG) support Programmable power reduction mode in each macrocell Slew rate control on individual outputs User programmable ground pin capability Extended pattern security features for design protection High-drive 24 mA outputs 3.3V or 5V I/O capability Advanced CMOS 5V FastFLASH technology Supports parallel programming of more than one XC9500 concurrently Available in 100-pin PQFP, 100-pin TQFP, and 160-pin PQFP packages
Description
The XC95144 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of eight 36V18 Function Blocks, providing 3,200 usable gates with propagation delays of 7.5 ns. See Figure 2 for the architecture overview.
Power Management
Power dissipation can be reduced in the XC95144 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for specific operating conditions using the following equation: ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f Where: MCHP = Macrocells in high-performance mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) Figure 1 shows a typical calculation for the XC95144 device.
600 (480)
* *
* * * * * * * * * *
H
erf igh P
orma
nce
Typical ICC (mA)
400 (320) (300) 200 (160)
Lo
wer w Po
0
50
100
DS067_01_110101
Clock Frequency (MHz)
Figure 1: Typical ICC vs. Frequency for XC95144
(c) 2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.
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XC95144 In-System Programmable CPLD
3 JTAG Port 1
JTAG Controller
In-System Programming Controller
36 I/O I/O I/O Fast CONNECT II Switch Matrix I/O 36 18 18
Function Block 1 Macrocells 1 to 18
Function Block 2 Macrocells 1 to 18
I/O Blocks I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR 2 I/O/GTS
36 18
Function Block 3 Macrocells 1 to 18
36 18
Function Block 4 Macrocells 1 to 18
36 18
Function Block 8 Macrocells 1 to 18
DS067_02_110101
Figure 2: XC95144 Architecture Function block outputs (indicated by the bold line) drive the I/O blocks directly.
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XC95144 In-System Programmable CPLD
Absolute Maximum Ratings
Symbol VCC VIN VTS TSTG TJ Description Supply voltage relative to GND Input voltage relative to GND Voltage applied to 3-state output Storage temperature (ambient) Junction temperature Value -0.5 to 7.0 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 -65 to +150 +150 Units V V V
oC oC
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Recommended Operation Conditions
Symbol VCCINT VCCIO Parameter Supply voltage for internal logic and input buffers Supply voltage for output drivers for 5V operation Commercial TA = 0oC to 70oC Industrial TA = Industrial TA = -40oC to +85oC Commercial TA = 0oC to 70oC -40oC to +85oC Min 4.75 4.5 4.75 4.5 3.0 0 2.0 0 Max 5.25 5.5 5.25 5.5 3.6 0.80 VCCINT + 0.5 VCCIO V V V V Units V
Supply voltage for output drivers for 3.3V operation VIL VIH VO Low-level input voltage High-level input voltage Output voltage
Quality and Reliability Characteristics
Symbol TDR NPE Data Retention Program/Erase Cycles (Endurance) Parameter Min 20 10,000 Max Units Years Cycles
DC Characteristic Over Recommended Operating Conditions
Symbol VOH VOL IIL IIH CIN ICC Parameter Output high voltage for 5V outputs Output high voltage for 3.3V outputs Output low voltage for 5V outputs Output low voltage for 3.3V outputs Input leakage current I/O high-Z leakage current I/O capacitance Operating supply current (low power mode, active) Test Conditions IOH = -4.0 mA, VCC = Min IOH = -3.2 mA, VCC = Min IOL = 24 mA, VCC = Min IOL = 10 mA, VCC = Min VCC = Max VIN = GND or VCC VCC = Max VIN = GND or VCC VIN = GND f = 1.0 MHz VI = GND, No load f = 1.0 MHz Min 2.4 2.4 Max 0.5 0.4 10 10 10 Units V V V V A A pF mA
160 (Typical)
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XC95144 In-System Programmable CPLD
AC Characteristics
XC95144-7 Symbol TPD TSU TH TCO fCNT(1) fSYSTEM(2) TPSU TPH TPCO TOE TOD TPOE TPOD TWLH TAPRPW Parameter I/O to output valid I/O setup time before GCK I/O hold time after GCK GCK to output valid 16-bit counter frequency Multiple FB internal operating frequency I/O setup time before p-term clock input I/O hold time after p-term clock input P-term clock output valid GTS to output valid GTS to output disable Product term OE to output enabled Product term OE to output disabled GCK pulse width (High or Low) Asynchronous preset/reset pulse width (High or Low) Min 4.5 0 125.0 83.3 0.5 4.0 4.0 7.0 Max 7.5 4.5 8.5 5.5 5.5 9.5 9.5 XC95144-10 Min 6.0 0 111.1 66.7 2.0 4.0 4.5 7.5 Max 10.0 6.0 10.0 6.0 6.0 10.0 10.0 XC95144-15 Min 8.0 0 95.2 55.6 4.0 4.0 5.5 8.0 Max 15.0 8.0 12.0 11.0 11.0 14.0 14.0 Units ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns ns
Notes: 1. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable. fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG. 2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs.
VTEST
R1 Device Output R2 CL
Output Type
VCCIO 5.0V 3.3V
VTEST 5.0V 3.3V
R1 160 260
R2 120 360
CL 35 pF 35 pF
DS067_03_110101
Figure 3: AC Load Circuit
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XC95144 In-System Programmable CPLD
Internal Timing Parameters
XC95144-7 Symbol Buffer Delays TIN TGCK TGSR TGTS TOUT TEN TPTCK TPTSR TPTTS TPDI TSUI THI TCOI TAOI TRAI TLOGI TLOGILP TF TLF TPTA(1) TSLEW Input buffer delay GCK buffer delay GSR buffer delay GTS buffer delay Output buffer delay Output buffer enable/disable delay 2.5 1.5 4.5 5.5 2.5 0 3.5 2.5 6.0 6.0 3.0 0 4.5 3.0 7.5 11.0 4.5 0 ns ns ns ns ns ns Parameter Min Max XC95144-10 Min Max XC95144-15 Min Max Units
Product Term Control Delays Product term clock delay Product term set/reset delay Product term 3-state delay 3.0 2.0 4.5 3.0 2.5 3.5 2.5 3.0 5.0 ns ns ns
Internal Register and Combinatorial Delays Combinatorial logic propagation delay Register setup time Register hold time Register clock to output valid time Register async. S/R to output delay Register async. S/R recover before clock Internal logic delay Internal low power logic delay 1.5 3.0 7.5 0.5 0.5 6.5 2.0 10.0 2.5 3.5 10.0 1.0 0.5 7.0 2.5 11.0 3.5 4.5 10.0 3.0 0.5 8.0 3.0 11.5 ns ns ns ns ns ns ns ns
Feedback Delays
FastCONNECT feedback delay Function block local feedback delay
-
8.0 4.0
-
9.5 3.5
-
11.0 3.5
ns ns
Time Adders Incremental product term allocator delay Slew-rate limited delay 1.0 4.0 1.0 4.5 1.0 5.0 ns ns
Notes: 1. TPTA is multiplied by the span of the function as defined in the XC9500 family data sheet.
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XC95144 In-System Programmable CPLD
XC95144 I/O Pins
Function Block 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 TQ100 PQ100 PQ160 - 11 12 - 13 14 - 15 16 - 17 18 - 19 20 - 22[1] - - 99[1] - - 1[1] 2[1] - 3[1] 4[1] - 6 7 - 8 9 - 10 - - 13 14 - 15 16 - 17 18 - 19 20 - 21 22 - 24[1] - - 1[1] - - 3[1] 4[1] - 5[1] 6[1] - 8 9 - 10 11 - 12 - 25 18 19 27 21 22 32 23 24 34 26 28 38 29 30 39 33[1] - 158 159[1] 3 5 2[1] 4[1] 7 6[1] 8[1] 9 11 12 14 13 15 16 17 - BScan Order 429 426 423 420 417 414 411 408 405 402 399 396 393 390 387 384 381[1] 378 375 372[1] 369 366 363[1] 360[1] 357 354[1] 351[1] 348 345 342 339 336 333 330 327 324 Function Block 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 TQ100 - 23[1] - - 24 25 - 27[1] 28 - 29 30 - 32 33 - 34 - - 87 - - 89 90 - 91 92 - 93 94 - 95 96 - 97 - PQ100 PQ160 - 25[1] - - 26 27 - 29[1] 30 - 31 32 - 34 35 - 36 - - 89 - - 91 92 - 93 94 - 95 96 - 97 98 - 99 - 43 35[1] 45 48 36 37 50 42[1] 44 52 47 49 53 54 56 55 57 - 132 140 147 149 142 143 150 144 145 151 146 148 153 152 154 155 156 - BScan Order 321 318[1] 315 312 309 306 303 300[1] 297 294 291 288 285 282 279 276 273 270 267 264 261 258 255 252 249 246 243 240 237 234 231 228 225 222 219 216
Notes: 1. Global control pin. Macrocell outputs to package pins subject to change, contact factory for latest information. Power, GND, JTAG, and Global Signals are fixed.
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XC95144 In-System Programmable CPLD
XC95144 I/O Pins (Continued)
Function Block 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 TQ100 PQ100 PQ160 - 35 - - 36 37 - 39 40 - 41 42 - 43 46 - 49 - - 74 - - 76 77 - 78 79 - 80 81 - 82 85 - 86 - - 37 - - 38 39 - 41 42 - 43 44 - 45 48 - 51 - - 76 - - 78 79 - 80 81 - 82 83 - 84 87 - 88 - 65 58 66 67 59 60 74 62 63 76 64 68 78 69 72 83 77 - - 117 119 123 122 124 125 126 129 128 133 134 130 135 138 131 139 - BScan Order 213 210 207 204 201 198 195 192 189 186 183 180 177 174 171 168 165 162 159 156 153 150 147 144 141 138 135 132 129 126 123 120 117 114 111 108 Function Block 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 TQ100 - 50 - - 52 53 - 54 55 - 56 58 - 59 60 - 61 - - 63 - - 64 65 - 66 67 - 68 70 - 71 72 - 73 - PQ100 PQ160 - 52 - - 54 55 - 56 57 - 58 60 - 61 62 - 63 - - 65 - - 66 67 - 68 69 - 70 72 - 73 74 - 75 - - 79 84 85 82 86 87 88 90 89 92 95 91 96 97 93 98 - - 101 105 107 102 103 109 104 106 112 108 111 114 113 115 118 116 - BScan Order 105 102 99 96 93 90 87 84 81 78 75 72 69 66 63 60 57 54 51 48 45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0
Notes: 1. Global control pin. Macrocell outputs to package pins subject to change, contact factory for latest information. Power, GND, JTAG, and Global Signals are fixed.
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XC95144 In-System Programmable CPLD
XC95144 Global, JTAG, and Power Pins
Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GTS3 I/O/GTS4 I/O/GSR TCK TDI TDO TMS VCCINT 5V VCCIO 3.3V/5V GND No Connects TQ100 22 23 27 3 4 1 2 99 48 45 83 47 5, 57, 98 26, 38, 51, 88 100, 21, 31, 44, 62, 69, 75, 84 - PQ100 24 25 29 5 6 3 4 1 50 47 85 49 7, 59, 100 28, 40, 53, 90 2, 23, 33, 46, 64, 71, 77, 86 - PQ160 33 35 42 6 8 2 4 159 75 71 136 73 10, 46, 94, 157 1, 41, 61, 81, 121, 141 20, 31, 40, 51, 70, 80, 99, 100, 110, 120, 127, 137, 160 -
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XC95144 In-System Programmable CPLD
Device Part Marking and Ordering Combination Information
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Device Type Package Speed Operating Range
XC95xxx TQ144 7C
This line not related to device part number
1
Sample package with part marking.
Device Ordering and Part Marking Number XC95144-7PQ100C XC95144-7PQG100C XC95144-7TQ100C XC95144-7TQG100C XC95144-7PQ160C XC95144-7PQG160C XC95144-10PQ100C XC95144-10PQG100C XC95144-10TQ100C XC95144-10TQG100C XC95144-10PQ160C XC95144-10PQG160C XC95144-10PQ100I XC95144-10PQG100I XC95144-10TQ100I XC95144-10TQG100I XC95144-10PQ160I XC95144-10PQG160I XC95144-15PQ100C XC95144-15PQG100C XC95144-15TQ100C XC95144-15TQG100C XC95144-15PQ160C XC95144-15PQG160C XC95144-15PQ100I XC95144-15PQG100I XC95144-15TQ100I XC95144-15TQG100I
Speed (pin-to-pin delay) 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 15 ns 15 ns 15 ns 15 ns 15 ns 15 ns 15 ns 15 ns 15 ns 15 ns
Pkg. Symbol PQ100 TQ100 TQG100 PQ160 PQ100 TQ100 TQG100 PQ160 PQ100 TQ100 TQG100 PQ160 PQ100 TQ100 TQG100 PQ160 PQ100 TQ100 TQG100
No. of Pins 100-pin 100-pin 100-pin 160-pin 100-pin 100-pin 100-pin 160-pin 100-pin 100-pin 100-pin 160-pin 100-pin 100-pin 100-pin 160-pin 100-pin 100-pin 100-pin
Package Type Plastic Quad Flat Pack (PQFP) Plastic Quad Flat Pack (PQFP); Pb-Free Thin Quad Flat Pack (TQFP) Thin Quad Flat Pack (TQFP); Pb-Free Plastic Quad Flat Pack (PQFP) Plastic Quad Flat Pack (PQFP); Pb-Free Plastic Quad Flat Pack (PQFP) Plastic Quad Flat Pack (PQFP); Pb-Free Thin Quad Flat Pack (TQFP) Thin Quad Flat Pack (TQFP); Pb-Free Plastic Quad Flat Pack (PQFP) Plastic Quad Flat Pack (PQFP); Pb-Free Plastic Quad Flat Pack (PQFP) Plastic Quad Flat Pack (PQFP); Pb-Free Thin Quad Flat Pack (TQFP) Thin Quad Flat Pack (TQFP); Pb-Free Plastic Quad Flat Pack (PQFP) Plastic Quad Flat Pack (PQFP); Pb-Free Plastic Quad Flat Pack (PQFP) Plastic Quad Flat Pack (PQFP); Pb-Free Thin Quad Flat Pack (TQFP) Thin Quad Flat Pack (TQFP); Pb-Free Plastic Quad Flat Pack (PQFP) Plastic Quad Flat Pack (PQFP); Pb-Free Plastic Quad Flat Pack (PQFP) Plastic Quad Flat Pack (PQFP); Pb-Free Thin Quad Flat Pack (TQFP) Thin Quad Flat Pack (TQFP); Pb-Free
Operating Range(1) C C C C C C C C C C C C I I I I I I C C C C C C I I I I
PQG100 100-pin
PQG160 160-pin PQG100 100-pin
PQG160 160-pin PQG100 100-pin
PQG160 160-pin PQG100 100-pin
PQG160 160-pin PQG100 100-pin
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XC95144 In-System Programmable CPLD
Device Ordering and Part Marking Number XC95144-15PQ160I XC95144-15PQG160I
Speed (pin-to-pin delay) 15 ns 15 ns
Pkg. Symbol PQ160
No. of Pins 160-pin
Package Type Plastic Quad Flat Pack (PQFP) Plastic Quad Flat Pack (PQFP); Pb-Free
Operating Range(1) I I
PQG160 160-pin
Notes: 1. C = Commercial: TA = 0 to +70C; I = Industrial: TA = -40 to +85C
Additional Information
XC9500 data sheets and application notes. Packages
Revision History
The following table shows the revision history for this document. Date 12/04/98 06/18/03 08/21/03 11/06/03 02/16/04 04/15/05 01/03/06 04/03/06 05/28/09 Version 4.0 5.0 5.1 5.2 5.3 5.4 5.5 5.6 5.7 Revision Update AC characteristics and internal parameters. Updated format. Updated Package Device Marking Pin 1 orientation. Update pin count on PQ160 packages. Correct GTS pin information by removing rows on GTS3 GTS4 from table on page 8. Add links to additional information. Added asynchronous preset/reset pulse width specification (TAPRPW). Added GTS3 and GTS4 pins to table on page 8. Added Warranty Disclaimer. Added Pb-Free package ordering information. Removed table note reference from Function Block 2, Macrocell 3 in XC95144 I/O Pins.
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS") ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS.
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